Liquid crystal display devices (LCDs) characterized by their thin design, light weight and low power consumption have come into widespread use in recent years and are utilized in the display units of mobile devices such as portable telephones (mobile telephones or cellular telephones), PDAs (Personal Digital Assistants) and laptop personal computers. Recently, however, liquid crystal display devices have come to be provided with large-size screens and techniques for dealing with moving pictures have become more advanced, thus making it possible to realize not only mobile applications but also stay-at-home large-screen display devices and large-screen liquid crystal televisions. Liquid crystal display devices that adopts an active matrix drive system and are capable of presenting a high-definition display are being utilized as these liquid crystal displays devices. The typical structure of an active-matrix liquid crystal display device will be described with reference to FIG. 37. The principal components connected to one pixel of a liquid crystal display unit are illustrated schematically by equivalent circuits in FIG. 37.
In general, a display unit 960 of an active-matrix liquid crystal display device comprises a semiconductor substrate on which transparent pixel electrodes 964 and thin-film transistors (TFTs) 963 are laid out in the form of a matrix (e.g., 1280×3 pixel columns×1024 pixels rows in the case of a color SXGA panel); an opposing substrate on the entire surface of which a single transparent electrode 966 is formed; and a liquid crystal material sealed between these two substrates arranged to oppose each other.
The TFT 963, which has a switching function, is turned on and off under the control of a scanning signal. When the TFT 963 is on, a grayscale signal voltage that corresponds to a video data signal is applied to the pixel electrode 964, and the transmittance of the liquid crystal changes owing to a potential difference between each pixel electrode 964 and opposing-substrate electrode 966. This potential difference is held by capacitance 965 of the liquid crystal even after the TFT 963 is turned off, as a result of which an image is displayed.
A data line 962 that sends a plurality of level voltages (grayscale signal voltages) applied to each pixel electrode 964 and a scan line 961 that sends the scanning signal are wired on the semiconductor substrate in the form of a grid (the data lines are 1280×3 in number and the scan lines are 1024 in number in the case of the above-mentioned color SXGA panel). The scan line 961 and data line 962 constitute a large capacitative load owing to the capacitance produced at the intersection of these lines and capacitance, etc., of the liquid crystal sandwiched between the opposing-substrate electrodes.
It should be noted that the scanning signal is supplied to the scan line 961 by a gate driver 970, and that the supply of grayscale signal voltage to each pixel electrode 964 is performed by a data driver 980 via the data line 962. Further, the gate driver 970 and data driver 980 are controlled by a display controller 950, a required clock CLK, control signals and power-supply voltage, etc., are supplied from the display controller 950, and video data is supplied from the display controller 950 to the data driver 980. At the present time, video is principally digital data.
Rewriting of one screen of data is carried out over one frame ( 1/60 of a second), data is selected sequentially every pixel row (every line) by each scan line, and a grayscale signal voltage is supplied from each data line within the selection interval.
Although the gate driver 970 need only supply at least a bi-level scanning signal, it is required that the data driver 980 drive the data lines by grayscale signal voltages of multiple levels that conform to the number of gray levels. To this end, the data driver 980 has a digital-to-analog converter (DAC) comprising a decoder for converting video data to a grayscale signal voltage and an operational amplifier for amplifying the grayscale signal voltage and outputting the amplified signal to the data line 962.
With the progress that has been made in raising image quality (increasing the number of colors) in liquid crystal display devices, there is now growing demand for at least 260,000 colors (video data of six bits per each of the colors R, G, B) and preferably 26,800,000 colors (video data of six bits per each of the colors R, G, B) or more. For this reason, a data driver that outputs a grayscale signal voltage corresponding to multiple-bit video data is such that the circuitry of the DAC is of larger scale. This increases the chip area of the data-driver LSI chip and invites an increase in cost. This problem will be elaborated below.
FIGS. 38A and 38B are diagrams illustrating an example of the structure of a conventional DAC used broadly and generally in liquid crystal display devices. FIG. 38A is a diagram illustrating the structure of a resistor-string DAC having an 8-bit input. The DAC includes a grayscale voltage generating circuit 811, a selector 812, a logic circuit 813 and an amplifier 815. The grayscale voltage generating circuit 811 outputs 256 grayscale voltages, which correspond to 8-bit data, from taps at each of the connection nodes of the resistor string across the ends of which a voltage is applied. The selector 812, which has switches, selects one grayscale voltage from among the 256 grayscale voltages. The amplifier 815 amplifies and outputs the grayscale voltage selected by the selector 812. The logic circuit 813 controls the switches of the selector 812 based upon 8-bit digital data input thereto.
FIG. 38B is a diagram illustrating the arrangement of a switch 812A (a switch comprising a P-channel transistor) of the selector 812 in FIG. 38A and a logic circuit 813A that controls the switch 812A. The logic circuit 813A can be implemented simply by an 8-input NAND gate to which the input is 8-bit digital data (B1, B2, B3, B4, B5, B6, B7 and B8) (inclusive of the bit complementary signals).
With the implementation shown in FIGS. 38A and 38B, 256 grayscale voltages produced by the grayscale voltage generating circuit 811 can be designed in conformity with the liquid-crystal gamma characteristic (the characteristic of liquid-crystal transmittance vs. applied voltage). Accordingly, the feature of this arrangement is that a high-quality display is possible.
If the number of gray levels increases, however, a problem that arises is an increase in the scale of the circuitry. Implementations shown in FIGS. 39 and 40 are known as methods of reducing area in an effort to solve this problem.
FIG. 39 illustrates an example of the structure of an 8-bit DAC obtained by combining a resistor-string DAC and a capacitor-array DAC. The side that is the resistor-string DAC comprises a reference voltage generating circuit 821, a selector 824 and a logic circuit 823 and operates based upon higher-order 4-bit data (B8, B7, B6 and B5) of 8-bit data (B8, B7, B6, B5, B4, B3, B2 and B1). The reference voltage generating circuit 821 outputs 17 reference voltages V1 to V17, switches Sna and Snb (where n is any number from 1 to 16) are selected by the selector 824, and reference voltages Vn and Vn+1 of mutually adjacent levels are output to terminals Na and Nb, respectively. The logic circuit 823 controls the switches of the selector 824 based upon the higher-order 4-bit data (B8, B7, B6 and B5).
The side that is the capacitor-array DAC comprises capacitance elements 835 to 839, switches 825 to 829, a logic circuit 822 and an amplifier 830 and operates based upon the lower-order 4-bit data (B4, B3, B2 and B1). Specifically, in terms of operation, first the switch 825 is turned on, changeover switches 826 to 829 are connected to the terminal Na, the voltage Vn at terminal Na is supplied to terminal Nc, and the voltages across the terminals of each of capacitance elements 835 to 839 are reset to zero. If switch 825 is thenceforth turned off and changeover switches 826 to 829 are connected to either one of terminals Na, Nb in accordance with the lower-order 4-bit data (B4, B3, B2 and B1), redistribution of electric charge occurs at terminal Nc, the potential at terminal Nc attains a prescribed voltage level that is the result of dividing voltages Vn and Vn+1 equally by 16, and this voltage is amplified and output by the amplifier 830. Accordingly, the DAC of FIG. 39 is capable of selecting a grayscale voltage of any of 256 gray levels by higher-order 4-bit data and lower-order 4-bit data.
The DAC of FIG. 39 is such that the number of voltages generated by the resistor string is 1/16 of the number in FIG. 38 and therefore the scale of the circuitry of the switches that select these signals and of the logic circuit 823 is reduced greatly in comparison with the implementation of FIG. 38. Further, the side of the capacitor-array DAC also can be realized with a comparatively diminished area. As a result, a feature of this DAC is that the overall DAC can be reduced greatly in terms of scale of the circuitry in comparison with the implementation of FIG. 38.
The method used in the arrangement of FIG. 39 is such that the reference voltages Vn and Vn+1 are sampled in parallel by the capacitor-array section in accordance with the digital data, and the grayscale voltages are obtained by the charge redistribution. On the other hand, a method of sampling reference voltages and obtaining grayscale voltages in a time serial is known. FIG. 40 is a diagram illustrating an example of the conventional structure of such a serial DAC.
The DAC shown in FIG. 40 includes two capacitors 844 and 845 each having one end connected to a ground (GND) terminal, the other ends being connected to terminals Nd and Ne, respectively; a changeover switch 841 for switchingly connecting the terminal Nd to either the GND terminal or supply terminal supplying a reference voltage VR; a switch 842 connected between the terminals Nd and Ne; a switch 843 connected between the terminal Ne and the GND terminal; and a voltage-follower circuit 846 comprising a differential amplifier having a non-inverting input terminal (+) connected to the terminal Ne and an inverting terminal (−) connected to an output terminal.
The operation of the circuit of FIG. 40 will now be described. Initially the switch 843 is turned on temporarily and the potential difference (terminal voltage) across the capacitor 845 is reset to zero.
Next, in accordance with the value of least-significant-bit data B1, either the reference voltage VR or ground GND is sampled at the terminal Nd by the changeover switch 841, after which the switch 841 is placed in the disconnected (open) state. The switch 842 is then turned on, charge redistribution occurs between the capacitors 844 and 845, the switch 842 is turned off and the charge is held in the capacitor 845.
Sampling is then performed by the switch 841 in accordance with the next bit of data B2, charge distribution occurs between the capacitors 844 and 845 owing to the switch 842 and the redistributed charge is thenceforth held in the capacitor 845.
Sample-and-hold is repeated in similar fashion in order from lower-order to higher-order bit data.
In case of K-bit data, one cycle of sample-and-hold is performed repeatedly K times. The voltage at terminal Ne at such time is as follows:VK=(2−1·BK+2−2·BK−1+ . . . +2−K·B1)·VR where BK, BK−1, . . . , B1 is 0 or 1. This voltage is amplified and output by the voltage-follower circuit 846.
As a result, the DAC of FIG. 40 is capable of outputting each of the voltage levels obtained by equally dividing the voltage across the reference voltage VR and ground GND into 2K voltage levels, in accordance with K-bit data.
Since the structure of the DAC shown in FIG. 40 is not dependent upon the number of data bits, a feature of the DAC is that the scale of the circuitry can be made very small irrespective of an increase in number of bits.
However, the output voltages of the DAC shown in FIG. 40 are linear outputs in which there are equal intervals between the voltage levels. With such an arrangement as it stands, grayscale voltages conforming to the gamma characteristic of liquid crystal cannot be produced.
Non-Patent Reference 2 proposes a method of constructing a DAC that makes possible linear outputs the number of which is several times the number of grayscale voltages necessary for output, and allocating grayscale voltages, which conform to the gamma characteristic of liquid crystal, from among these multiple linear output levels.
This method increases by two to three bits the number of bits that correspond to the number of grayscale voltages that are actually output. This means that the DAC of FIG. 40, which is independent of the number of bits, is ideal.
FIG. 41 is a serial DAC the structure of which raises the accuracy of the structure shown in FIG. 40. This DAC has a function that compensates for offset of the voltage-follower circuit.
The DAC shown in FIG. 41 includes a differential amplifier 856 having a non-inverting input terminal (+) to which a reference voltage Vref is applied and an inverting input terminal (−) to which the terminal Nf is connected; two capacitors 854 and 855, each having one end connected to terminal Nf, the other ends being connected to terminals Ng, Nh, respectively; a switch 851 connected to the terminal Ng for selecting either a supply terminal of reference voltage VI or a supply terminal of reference voltage VR; a switch 852 connected between the terminals Ng and Nh; a switch 853 connected between the supply terminal of reference voltage VI and terminal Nh; a switch 857 connected between the output terminal of a differential amplifier 856 and terminal Nf; and a switch 858 connected between the output terminal of the differential amplifier 856 and terminal Nh. Capacitance values Cs and Ch of the capacitors 854 and 855 usually are set to be equal, i.e., Cs=Ch.
The operation of the circuit of FIG. 41 will now be described. Initially the switches 857 and 858 are turned on and off, respectively. If the differential amplifier 856 has an offset Δ, then voltage VNf at terminal Nf is made VNf=Vref+Δ.
Next, the switch 853 is turned on temporarily and the potential at terminal Nh is reset to the reference voltage VI.
In accordance with the value of least-significant-bit data B1, either the reference voltage VR or reference voltage VI is sampled at the terminal Nd by the switch 851, after which the switch 851 is placed in the disconnected state.
The switch 852 is then turned on, charge redistribution occurs between the capacitors 854 and 855, the switch 852 is turned off and the redistributed charge is held in the capacitor 855.
Sample-and-hold is repeated in similar fashion in order from lower-order to higher-order bit data. In case of K-bit data, one cycle of sample-and-hold is performed repeatedly K times. The voltage at terminal Nh at such time is as follows:VK=(2−1·BK+2−2·BK−1+ . . . +2−K·B1) . . . (VR−VI)+VI where BK, BK−1, . . . , B1 is 0 or 1. The principle of this operation is similar to that of FIG. 40.
The potential difference (terminal voltage) across the capacitor 855 at this time is (VK−VNf).
Next, switches 857 and 858 are turned off and on, respectively. The terminal Nh is connected to the output terminal of the differential amplifier 856 and the output voltage Vout becomesVout=VNf+(VK−VNf)=VK Thus an output voltage that is not dependent upon the offset Δ can be obtained.
It should be noted that FIGS. 38, 39 and 40 correspond to FIGS. 5-33, 5-38 and 5-42, respectively, of Non-Patent Document 1, and FIG. 41 corresponds to FIGS. 1 and 2 of Patent Document 1. These introduce the respective principles.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-59-154820
[Patent Document 2]
U.S. Pat. No. 6,246,451 (FIG. 2)
[Non-Patent Document 1]
Kindai Kagakusha “Ultra LSI Introduction Series 5; Foundations of MOS Integrated Circuits” pp. 157-167 (FIGS. 5-33)
[Non-Patent Document 2]
SOCIETY FOR INFORMATION DISPLAY 2004; INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS; VOLUME XXXV pp. 1556-1559
The arrangement shown in FIGS. 38A and 38B is disadvantageous in that an increase in the number of bits leads to an increase in number of elements and invites an increase in area.
The arrangement shown in FIG. 39 is disadvantageous in that it uses a large number of capacitance elements and therefore is susceptible to the effects of a variance in capacitance value from one capacitance element to another, parasitic capacitance in the transistor switches that select the capacitance elements, and switching noise, etc. Output error tends to occur as a result.
The arrangements of FIGS. 40 and 41 employ only two capacitance elements. However, since the number of cycle operations is equivalent to the number of data bits, a very small output error caused by variance in the capacitance values and by parasitic capacitance in the transistor switches, which occur in one cycle, accumulates over a number of cycles and tends to increase.
Further, since real driving time is curtailed by the cycle time, these arrangements are difficult to apply to the data driver of a large-screen, high-definition display device having a high data-line load and a short data driving time for one item of data.